1. Field of the Invention
This invention relates to an improved method of making a bipolar transistor for an integrated circuit structure. More particularly, this invention relates to a method for making an improved fully self-aligned bipolar transistor.
2. Description of the Prior Art
Conventional bipolar transistors are usually formed with a buried layer leading from the collector region in the substrate to a sinker or vertical doped region which interconnects the buried layer with a collector contact on the surface of the substrate. The sinker is usually separated from the active region of the transistor by a field oxide region typically about 2-4 microns wide.
Typical of such prior art structures are those shown in an article by Vora et al entitled "A Sub100 Picosecond Bipolar ECL Technology" published at pp 34-37 in IEDM in 1985 and in an article by Ning et al entitled "Self-Aligned Bipolar Transistors for High-Performance and Low-Power-Delay VLSI" published at pp 1010-1013 of the IEEE Transactions On Electron Devices, Vol. ED-28, No. 9, September, 1981.
Such a prior art construction is also illustrated in FIG. 1 wherein a buried layer A is formed in a substrate and isolation slots D which extend through buried layer A separate the transistor from other devices in or on the substrate. A collector region F is formed above buried layer A. Above collector region F are intrinsic base region G and extrinsic base region H. An emitter region I above intrinsic base region G is connected to the emitter contact E. Base contact B interconnects with extrinsic base H through a conductive polysilicon layer J. Oxide layer K separates base contact B from emitter contact E.
In such a construction, connection is made between collector region F and collector contact C through buried layer A and a sinker S which usually comprises a portion of the substrate which is highly doped to increase the conductivity of the sinker to provide a low resistance path between the buried layer and the collector contact. To isolate this sinker from the active portions of the device and to prevent or inhibit migration of the dopants in the sinker to the active regions of the device, a portion of the field oxide L is usually formed at LL between sinker S and the active regions. Since field oxide portion LL is usually about 2-4 microns wide, its presence adds considerably to the overall area or footprint occupied by the transistor. Advances in lithography have permitted line width resolution to reach micron dimensions and processing techniques have improved to the point where the reliable formation of thin films and precise etching are both possible so that smaller and more predictable feature sizes can be obtained. As a consequence, the lateral dimensions of devices are reaching micron levels and passing on into nanometer ranges resulting in a continued decrease in the ensuing density of integrated circuits.
Thus, a greater number of individual devices can be fabricated in a given area. While further increases in areal density are likely, physical, equipment, and process limits are being approached. In addition, as devices become smaller and smaller, their power ratings are reduced and the relative importance of problems such as parasitic capacitance and contamination is increased. Due to the diminishing return to be obtained from further efforts to improve areal density, it has become desirable to consider the possibility of increasing the extent of the active regions in the vertical dimension to thereby obtain performance for a device with established lateral dimensions which is equivalent to the performance of a device with greater lateral dimensions. Also higher power or higher performance devices may be obtained in this way.
As the densities of integrated circuits have increased, there has been serious consideration of using trench or slot formation processes for forming the insulating zones between individual transistors. Such an isolation technique is described in Bondur et al U.S. Pat. No. 4,104,086. This isolation technique is also described in Bonn U.S. patent application Ser. No. 719,085 and Gwozdz U.S. patent application Ser. No. 759,621, both of which applications are assigned to the assignee of this application.
Another form of slot isolation is shown in Roberson U.S. Pat. No. 3,913,124 wherein a V shaped isolation slot is formed having isolation oxide formed on the sloped sidewalls with the collector extent or sinker comprising an epitaxial silicon formed to extend down through the middle of one portion of the slot.
In addition to forming slots in semiconductor wafers for isolating individual devices, slots have also been considered for use as passive circuit elements. For example, it has been proposed that a slot be filled with an appropriate material so that it will function as a capacitor. See, e.g., K. Minegishi et al., "A Sub-Micron CMOS Megabit Level Dynamic RAM Technology Using a Doped Face Trench Capacitor Cell", Proceedings, IEDM, 1983, p. 319; and T. Morie et al., "Depletion Trench Capacitor Technology for Megabit Level MOSdRAM", IEEE Electron Device Letters, v. EDL-4, No. 11, p. 411, Nov. 1983. Such applications are possible because, with appropriate filling materials, a slot can be made to be conductive or insulating as required.
It has also been proposed to construct active devices in slots in a substrate. Fujitsu Japanese Patent Document 57-11150 discloses construction of a lateral bipolar transistor wherein an emitter region is formed by diffusing impurities into the walls of a slot formed in a substrate. A collector region is similarly formed using a slot formed in the substrate near the first slot. The substrate portion between the emitter region slot and the collector region slot is said to form the base of the transistor.
The construction of an active device in slots in a substrate is also disclosed and claimed in Bowers U.S. patent application Ser. No. 576,659, assigned to the assignee of this invention, wherein an emitter slot for a bipolar transistor is formed in a substrate and a base region is diffused into the substrate through the walls of the emitter slot with a collector slot formed in the substrate spaced from the emitter slot and base region.
An integrated circuit structure construction comprising slots having oxide coatings on the upper portions of the walls thereof is shown in Arnold et al U.S. Pat. No. 4,520,552.
A slot collector transistor and the method of forming same are both described and respectively claimed in Iranmanesh et al U.S. patent application Ser. No. 740,361 and Iranmanesh et al U.S. patent application Ser. No. 711,701, both assigned to the assignee of this invention.